1. Field of the Invention
The present invention relates to a output buffer circuit, and more specifically to a output buffer circuit used in an interface for transferring a high speed signal between LSIs.
2. Description of Related Art
With a recent advancement of a multi-function and a low power consumption of systems, an interface between LSIs (large scaled integrated circuits) are required to be a high speed and a small amplitude. In order to realize a high speed interface, it is necessary to make the amplitude of an output waveform small. However, since the amplitude is determined by a ground potential or a power supply potential as a reference, an internal operation threshold becomes different from an output signal threshold, with the result that a time ratio between a high level period and a low level period of the output signal waveform cannot be maintained at 1:1 (50%), and becomes apt to greatly vary. In addition, since many functions are incorporated in one LSI, the number of pins of a LSI package becomes large, and therefore, a noise becomes a problem at a testing time because a plurality of buffers operate concurrently. In order to avoid this problem, a noise suppressing circuit is inserted, but this circuit becomes a cause attributable to change of the duty ratio of the output signal waveform.
The change of the duty ratio is a factor lowering the data transfer speed. Therefore, in order to realize a high speed interface so as to elevate performance of the system, it is necessary to maintain the duty ratio of the output signal waveform of an output buffer around 50%
Referring to FIG. 5, there is shown, as an example of a first prior art output buffer circuit, a circuit of a buffer circuit of a HSTL (high speed transceiver logic) interface standardized by E1A/JEDEC, which is recently used as one of interfaces for transferring a high speed signal between semiconductor integrated circuits. This first prior art output buffer circuit includes an inverter 1 responding to an input signal H01 to generate an inverted signal "a", an inverter 9 responding to an input signal TEST to generate an inverted signal "d", an inverter 2 responding to the signal "a" to generate an inverted signal "b", an inverter 3 responding to the signal "b" to generate an inverted signal P11, a transfer gate 4 formed of a P-channel transistor having a gate receiving the input signal TEST and an N-channel transistor having a gate receiving the inverted signal "d" for controlling passage/block of the signal P11 in accordance with the level of the signal TEST so as to output a signal P12, and a P-channel transistor MP5 having a drain receiving the signal P12, and a gate receiving the signal "d" and a source connected to a 2.5 V power supply voltage.
The first prior art output buffer circuit further includes an inverter 6 receiving the signal "a" to generate an inverted signal "d", an inverter 7 responding to the signal "c" to generate an inverted signal P13, a transfer gate 8 formed of a P-channel transistor having a gate receiving the input signal TEST and an N-channel transistor having a gate receiving the inverted signal "d" for controlling passage/block of the signal P13 in accordance with the level of the signal TEST so as to output a signal P14, and an N-channel transistor MN5 having a drain receiving the signal P14, and a gate receiving the signal TEST and a source connected to ground. Furthermore, the first prior art output buffer circuit includes a P-channel transistor MP10 having a gate receiving the signal P12, a source connected to a 1.5 V power supply voltage, and a drain for outputting an output signal N01, an N-channel transistor MN10 having a gate receiving the signal P14, a source connected to the ground and a drain connected to the drain of the P-channel transistor MP10, a P-channel transistor MP11 having a gate receiving the signal P11, a source connected to the 1.5 V power supply voltage, and a drain connected to the drain of the P-channel transistor MP10, and an N-channel transistor MN11 having a gate receiving the signal P13, a source connected to the ground and a drain connected to the drain of the P-channel transistor MP10. The inverters 1 to 3, 6, 7 and 9 are driven with the 2.5 V power supply voltage.
In addition, the transistors MP10 and MN10 constitute an inverter 10, and the transistors MP11 and MN11 constitute an inverter 11.
Now, an operation of the first prior art output buffer circuit will be described with reference to FIG. 5. First, when the input signal TEST is at a low level, the transfer gates 4 and 8 are on, and the transistors MP5 and MN5 are off. Therefore, the input signal H01 is supplied to the inverter 10 formed of the transistors MP10 and MN10, an to the inverter 11 formed of the transistors MP11 and MN11, so that these inverters 10 and 11 output the output signal N01 in accordance with the input signal H01.
On the other hand, when the input signal TEST is at a high level, the transfer gates 4 and 8 are off, and the transistors MP5 and MN5 are on, so that the transistors MP10 and MN10 of the inverter 10 are rendered off. Accordingly, the output signal N01 in accordance with the input signal H01 is outputted by only the inverter 11, namely, only the transistors MP11 and MN11. Therefore, the driving power is lowered, so that a switching noise is suppressed.
Next, an operation waveform of the first prior art output buffer circuit will be described in detail with reference to FIGS. 6A and 6B, which are timing charts showing various operation waveforms of the first prior art output buffer circuit.
When the input signal H01 is brought to the high level, after the signal P11 inputted to the gate of the transistor MP11 is brought to the low level, the signal P12 inputted to the gate of the transistor MP10 is brought to the low level. Simultaneously, after the signal P13 inputted to the gate of the transistor MN11 is brought to the low level, the signal P14 inputted to the gate of the transistor MN10 is brought to the low level. This is because the potential of the signal P11 is transferred through the transfer gate 4 as the signal P12 and the potential of the signal P13 is transferred through the transfer gate 8 as the signal P14.
In the HSTL interface, a terminating method of a transmission path is divided into four classes (class 1 to class 4). Referring to FIG. 7 which is a block diagram for illustrating the construction of the HSTL class-2 interface, this HSTL class-2 interface includes an output buffer 101 driven with a 1.5 V power supply voltage to output an output signal N01 in accordance with an input signal H01, a resistor 102 of a resistance of 50.OMEGA. having one end connected to a 0.75 V power supply voltage and the other end connected to the output of the output buffer 101, a transmission path 104 having an impedance of 50.OMEGA. and one end connected to the output of the output buffer 101, another resistor 103 of a resistance of 50.OMEGA. having one end connected to a 0.75 V power supply voltage and the other end connected to the output of the transmission path 104, and a differential amplifier 105 having a non-inverted input connected to the output of the transmission path 104, an inverted input connected to a reference signal Vref of 0.75 V. Here, the output buffer 101 is constituted of the first prior art output buffer circuit mentioned above or a second prior art output buffer circuit which will be described hereinafter.
Referring to FIG. 8, which is a timing chart illustrating input and output signal waveforms in the HSTL class-2 interface using the first prior art output buffer circuit as the output buffer 101, since the output of the output buffer 101 is connected to the resistors 102 and 103 clamped to 0.75 V, the output signal N01 of the output buffer 101 can obtain the amplitude of 0 V to 1.5 V.
Referring to FIG. 9, there is shown a circuit diagram of the second prior art output buffer circuit used in the HSTL interface. In FIG. 9, elements similar to those shown in FIG. 5 are given the same Reference Numerals and Signs, and explanation will be omitted. This second prior art output buffer circuit includes, in addition to the inverters 1, 2, 3, 6, 7, 9, 10 and 11 in common to the first prior art output buffer circuit, a two-input NOR gate 12 receiving the input signal TEST and the output signal "a" of the inverter 1 for outputting a NOR output signal "f", an inverter 13 responding to the signal "f" to output an inverted signal "g" to the gate of the transistor MP11 of the inverter 11, a two-input NAND gate 14 receiving the output signal "d" of the inverter 9 and the signal "a" for outputting a NAND output signal "h", and an inverter 15 responding to the signal "h" to output an inverted signal "i" to the gate of the transistor MN11 of the inverter 11. In addition, the output signal P11 of the inverter 3 is supplied directly to the gate of the transistor MP10 of the inverter 10, and the output signal P14 of the inverter 7 is applied directly to the gate of the transistor MN10 of the inverter 10. The inverters 1 to 3, 6, 7, 9, 13 and 15, the NOR gate 12 and the NAND gate 14 are driven with the 2.5 V power supply voltage.
Now, an operation of the second prior art output buffer circuit will be described with reference to FIG. 9. First, when the input signal TEST is at the low level, the NOR gate 12 responds to the low level of this signal TEST received at its one input, to output the inverted signal "f" of the inverted signal "a" of the input signal H01 received at its other input. On the other hand, the NAND gate 14 responds to the high level of the signal TEST received at its one input, to output the inverted signal "h" of the input signal H01 received at its other input. Accordingly, the inverters 10 and 11 output the output signal N01 corresponding to the input signal H01.
When the input signal TEST is at the high level, the NOR gate 12 outputs the signal "f" of the low level in response to the high level of the signal TEST, and the NAND gate 14 outputs the signal "h" of the high level in response to the low level of the inverted signal "d" of the signal TEST. Accordingly, the transistors MP11 and MN11 of the inverter 11 are rendered off, so that the output signal N01 corresponding to the input signal H01 is outputted by only the inverter 10. Thus, the driving power is lowered, so that the switching noise is suppressed.
Referring to FIG. 10, there is shown a circuit diagram of a third prior art output buffer circuit, which is a buffer circuit of a SSTL (stub series terminated logic) interface standardized by E1A/JEDEC, and which is recently used as one of interfaces for transferring a high speed signal between semiconductor integrated circuits, similarly to the first and second prior art output buffer circuits. In FIG. 10, elements similar to those shown in FIG. 5 are given the same Reference Numerals and Signs, and explanation will be omitted.
This third prior art output buffer circuit includes, in addition to the inverters 1, 3, 7, 9, 10 and 11, the transfer gates 4 and 8, and the transistors MP5 and MN5 in common to the first prior art output buffer circuit, level shift circuits 22 and 26 receiving the output signal "a" of the inverter 1 for outputting predetermined level-shifted signals "j" and "k" to the inverters 3 and 7, respectively.
The inverter 1 is driven with the 2.5 V power supply voltage, and the other inverters 3, 7, 9, 10 and 11, the transfer gates 4 and 8, and the transistors MP5 and MN5 are driven with a 3.3 V power supply voltage.
Now, an operation of the third prior art output buffer circuit will be described with reference to FIG. 10. First, when the input signal TEST is at the low level, the transfer gates 4 and 8 are rendered on and the transistors MP5 and MN5 are rendered off, similarly to the first prior art output buffer circuit. Accordingly, the input signal H01 is supplied to the inverter 10 formed of the transistors MP10 and MN10 and the inverter 11 formed of the transistors MP11 and MN11, so that these inverters 10 and 11 output the output signal N01 in accordance with the input signal H01.
On the other hand, when the input signal TEST is at a high level, the transfer gates 4 and 8 are off, and the transistors MP5 and MN5 are on, so that the transistors MP10 and MN10 of the inverter 10 are rendered off. Accordingly, the output signal N01 in accordance with the input signal H01 is outputted by only the inverter 11, namely, only the transistors MP11 and MN11. Therefore, the driving power is lowered, so that a switching noise is suppressed.
This third prior art output buffer circuit is so configured to have an internal macro power supply voltage of 2.5 V, which is lower than 3.3 V of the output voltage, in order to reduce the power consumption of the LSI. Because of this, the output buffer requires the level shifting circuits 22 and 26 in order to elevate from 2.5 V to 3.3 V.
Referring to FIG. 11, which is a circuit diagram showing the construction of the level shift circuit 22, this level shift circuit 22 includes a P-channel transistor MP21 having a gate receiving the input signal "a", a source connected to the 2.5 V power supply voltage and a drain for outputting a signal P01, an N-channel transistor MN21 having a gate receiving the input signal "a", a source connected to ground and a drain connected to the drain of the transistor MP21, an N-channel transistor MN22 having a gate connected to the drain of the transistor MP21, a source connected to the ground and a drain for outputting a signal P02, a P-channel transistor MP22 having a gate receiving the output signal "j", a source connected to the 3.3 V power supply voltage and a drain connected to the drain of the transistor MN22, a P-channel transistor MP23 having a gate connected to the drain of the transistor MP22, a source connected to the 3.3 V power supply voltage and a drain for outputting the output signal "j", and an N-channel transistor MN23 having a gate receiving the input signal "a", a source connected to the ground and a drain connected to the drain of the transistor MP23.
Now, an operation of the level shift circuit 22 will be described with reference to FIG. 11 and FIG. 12 which illustrates operating waveforms of various points. When the input signal "a" is brought to a high level (2.5 V), the transistor MN23 is turned on. At this time, the transistor MP23 of the last stage is also turned on, but since the size of the transistor MN23 is larger than that of the transistor MP23, a path-through current flows through the transistors MP23 and MN23, so that the output signal "J" becomes lower than a threshold of a next stage block, namely, becomes a low level. Thereafter, when the signal P02 reaches the high level of 3.3 V, the path-through current stops.
Then, when the input signal "a" is brought to the low level, the signal P01 is brought to the high level (2.5 V), and the transistor MN22 is turned on so that the signal P02 is brought to the low level, and therefore, the transistor MP23 is turned on. At this time, since the transistor MN23 has been turned off, the output signal "j" becomes the high level (3.3 V). Accordingly, a time TpdLH from the moment the input signal "a" is brought to the low level to the moment the output signal "j" is brought to the high level is longer than a time TpdHL from the moment the input signal "a" is brought to the high level to the moment the output signal "j" is brought to the low level. Namely, a delay time is long.
In accordance with the method for terminating the transmission path, the SSTL interface is divided into two classes (class 1 and class 2). Referring to FIG. 13, which a block diagram for illustrating the construction of the SSTL class-2 interface, this SSTL class-2 interface includes an output buffer 201 driven with a 3.3 V power supply voltage to output an output signal N01 in accordance with an input signal H01, a resistor 202 of a resistance of 50.OMEGA. having one end connected to the output of the output buffer 201, a transmission path 204 having an impedance of 50.OMEGA. and one end connected to the other end of the resistor 202, another resistor 203 of a resistance of 25.OMEGA. having one end connected to a 1.5 V power supply voltage and the other end connected to the output of the transmission path 204, and a differential amplifier 205 having a non-inverted input connected to the output of the transmission path 204, an inverted input connected to a reference signal Vref of 1.5 V. Here, the output buffer 201 is constituted of the third prior art output buffer circuit mentioned above.
Even in this case, similarly to the first prior art output buffer circuit, the output signal N01 of the output buffer 201 can obtain the amplitude of 0 V to 3.3 V because of the resistor 202 connected to the output N01 of the output buffer 201 and the resistor 203 connected to the resistor 202 and clamped to 1.5 V.
A first problem of the first, second and third prior art output buffer circuits as mentioned above is that in the output signal of the first, second and third prior art output buffer circuits which are high speed buffers, since the duty ratio (the ratio between the high level period and the low level period) changes from 50% (called a "duty distortion" hereinafter), if the operating frequency is elevated, the level change occurs in the level having a shorter period so that a waveform distortion occurs, and in an extreme cases the output waveform disappears. Thus, the speed-up cannot be realized.
The reason for this is as follows: In the high speed buffer of the HSTL interface such as the first and second prior art output buffer circuits, the power supply voltage of the final stage inverter is 1.5 V, but in for example a 0.25 .mu.m process, the power supply voltage of a pre-buffer is 2.5 V which is higher than 1.5 V. Therefore, at the rising time of the output signal of the buffer, the threshold of the final stage inverter is lower than the output signal waveform of the pre-buffer, and therefore, a long time is required until the output signal level of the pre-buffer becomes lower than the threshold of the final stage inverter. Namely, the delay time of the buffer becomes large. On the other hand, at a falling time of the output signal of the buffer, the output signal level of the pre-buffer immediately becomes higher than the threshold of the final stage inverter, and therefore, the delay time is small. Thus, the duty ratio of the output signal waveform becomes out of 50%.
Therefore, in order to effectively equalize the delay time in the rising and the delay time in the falling of the buffer output signal, it may be considered to adjust the size ratio between the P-channel transistor and the N-channel transistor in the output stage of the pre-buffer so as to minimize the duty distortion. However, since the difference between the pre-buffer output signal level and the threshold of the final stage inverter is as large as about 0.5 V, it is not possible to completely prevent the duty distortion of the output signal waveform.
In addition, in the high speed buffer as in HSTL, since the high level and the low level of the input and the output are prescribed in a DC standard, it is impossible to adjust the duty ratio by adjusting the size ratio between the P-channel transistor and the N-channel transistor in the output stage of the output buffer, since this results in change of the DC level. Accordingly, the duty distortion cannot be prevented by this adjustment of the size ratio.
Furthermore, in the buffer such as the first prior art output buffer circuit having the driving power control circuit for reducing the switching noise at the testing time, since the transfer gate is inserted between the pre-buffer and the final stage inverter, the output signal waveform of the pre-buffer is blunted by the on-resistance of the transfer gate so that the duty ratio changes. Therefore, if the size of the transfer gate is enlarged to reduce the on-resistance of the transfer gate, the diffused capacitance becomes large, with the result that the signal waveform of the pre-buffer is further blunted.
In the high speed buffer of the SSTL interface such as the third prior art output buffer circuit, the power supply voltage of the final stage inverter is 3.3 V, but in for example a 0.25 .mu.m process, the power supply voltage of the pre-buffer is 2.5 V which is lower than 3.3 V. Therefore, the level shift circuit for elevating from 2.5 V to 3.3 V. However, since the signal transfer path is different between the high level outputting time and the low level outputting time as mentioned above, the delay time is greatly different. In addition, since the high level and the low level of the input and the output in the SSTL buffer are prescribed in the DC standard similarly to the HSTL, the duty distortion cannot be improved by adjusting the size ratio between the P-channel transistor and the N-channel transistor in the final state inverter.
In the first, second and third prior art output buffer circuits as mentioned above, because the internal operation threshold is different from the threshold of the output signal, because there is inserted the circuit for reducing the noise in the concurrent operation of a plurality of buffers at the testing time in an LSI package having a number of pins, the duty ratio of the output signal waveform (the ratio between the high level period and the low level period) changes from 50% (called a "duty distortion" hereinafter). Therefore, if the operating frequency is elevated, the level change occurs in the level having a shorter period so that a waveform distortion occurs, and in an extreme case, the output waveform disappears. Thus, the speed-up cannot be realized.